A. Padilla

Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield

Geoffrey W. Burr, Kumar Virwani, Rohit S. Shenoy et al. · 2012 · 71 citations

Engineering, Electrical Engineering, Materials Science +15

Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials

Kumar Virwani, Geoffrey W. Burr, Rohit S. Shenoy et al. · 2012 · 64 citations

Engineering, Electrical Engineering, Materials Science +17

Programming characteristics of the steep turn-on/off feedback FET (FBFET)

Chun Wing Yeung, A. Padilla, Tsu‐Jae King Liu et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Electrical Engineering, Microelectronics +15

Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials

Rohit S. Shenoy, G. Kalpana, Bryan L. Jackson et al. · Symposium on VLSI Technology · 2011 · 32 citations

Engineering, Electrical Engineering, Materials Science +17

Voltage polarity effects in GST-based phase change memory: Physical origins and implications

A. Padilla, Geoffrey W. Burr, Kumar Virwani et al. · 2010 · 25 citations

Engineering, Materials Engineering, Materials Science +16