Riza Tamer Cakici

Gate leakage reduction for scaled devices using transistor stacking

Subhas Chandra Mukhopadhyay, C. Neau, Riza Tamer Cakici et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 153 citations

Hardware Security, Device Modeling, Electrical Engineering +11

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Animesh Datta, Ashish Goel, Riza Tamer Cakici et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 80 citations

Device Modeling, Low-power Electronics, Electrical Engineering +14

Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

Riza Tamer Cakici, Kaushik Roy · IEEE Transactions on Electron Devices · 2007 · 32 citations

Low-power Electronics, Double-gate Mos, Electrical Engineering +15

Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks

Paul E. Nicollian, Riza Tamer Cakici, Anand Krishnan et al. · IEEE Transactions on Electron Devices · 2011 · 11 citations

Device Modeling, Electrical Engineering, Engineering +13