Chao-Wen Tzeng

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

Chao-Wen Tzeng, Shi‐Yu Huang, Pei-Ying Chao · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 43 citations

Engineering, Hardware Verification Language, Compiler Technology +23

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test

Chao-Wen Tzeng, Shi‐Yu Huang · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009 · 31 citations

Engineering, Computer Architecture, High Performance Computing +18

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

Chao-Wen Tzeng, Shi‐Yu Huang · IEEE Design & Test of Computers · 2008 · 27 citations

Engineering, Computer Architecture, Test Data Generation +18

A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains

Edward W. Hsu, Shi‐Yu Huang, Chao-Wen Tzeng · 2006 · 16 citations

Robust New Paradigm, Engineering, Verification +19

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

Pei-Ying Chao, Chao-Wen Tzeng, Shi‐Yu Huang et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2012 · 12 citations

Engineering, Clock Recovery, Significant Jitter +9