This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves ${-}$ 61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves ${-}$ 54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is ${<}{-}$ 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm $^{2}$ .

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	3	3	162
2	Engineering	1	1	37
3	Microelectronics	1	1	37

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