A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

Abstract

A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.