Rachael J. Parker

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders et al. · 2014 · 241 citations

Engineering, Computer Engineering, Electrical Engineering +17

A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS

N.J. August, Hyung‐Jin Lee, Martin Vandepas et al. · 2012 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, S. Biswas, Markus J. Buehler et al. · 2008 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

Cascaded PLL design for a 90nm CMOS high performance microprocessor

K.L. Wong, Eyal Fayneh, Ernest Knoll et al. · 2003 · 26 citations

Engineering, Computer Engineering, Electrical Engineering +15

Entropy justification for metastability based nondeterministic random bit generator

Rachael J. Parker · 2017 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +15