R. Kho

Processor-based built-in self-test for embedded DRAM

J. Dreibelbis, J. Barth, H.L. Kalter et al. · IEEE Journal of Solid-State Circuits · 1998 · 84 citations

Hardware Security, Memory Architecture, Engineering +14

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

R. Kho, David Boursin, M. Brox et al. · IEEE Journal of Solid-State Circuits · 2010 · 38 citations

Engineering, Vlsi Design, Hardware Acceleration +14

An ASIC library granular DRAM macro with built-in self test

J. Dreibelbis, J. Barth, R. Kho et al. · 2002 · 31 citations

Engineering, Mem Testing, Computer Architecture +20

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques

R. Kho, David Boursin, M. Brox et al. · 2009 · 15 citations

Memory Interfaces, Electrical Engineering, Memory Architecture +14