75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques

Abstract

Memory interfaces for high-speed graphics systems have reached the 4 to 6 Gb/s/pin regime with GDDR4 and the introduction of GDDR5 [1–4] at chip densities up to 512Mb. To satisfy the demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. In this paper, a 7Gb/s/pin 1Gb GDDR5 DRAM with an array architecture for fast column access, a boosting transmitter, multiple voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INT</inf> ) domains to control on chip power noise, and a high-speed internal V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INT</inf> power generator system are presented. This 1Gb GDDR5 memory device is fabricated in a conventional 75nm DRAM process and characterized for a 7Gb/s/pin data transfer rate at 1.5V.