Chinese Journal of Electronics · 2010 · 33 citations · 14 references
Energy ConsumptionSystem On ChipEngineeringEvolvable HardwareEdge ComputingRouter ArchitectureComputer EngineeringComputer ArchitectureSystems EngineeringNetwork On ChipRouter DesignGenetic AlgorithmInterconnection Network ArchitectureRouting ApproachChip ArchitecturesNoc ArchitectureEnergy-efficient Networking
A genetic algorithm based mapping and routing approach called GAMR is proposed for low energy design of 2D mesh based Network on chip (NoC) under communication bandwidth constraint. The aim is to min- imize total communication energy consumption and max- imum link bandwidth of the NoC architecture. GAMR automatically maps IP cores of given application onto NoC architecture and generates a deterministic deadlock- free minimal routing path for each communication trace. The evaluation performed on various multimedia bench- mark applications conflrms the e-ciency of the proposed approach. Experimental results show that GAMR saves about 20% of energy consumption and 30% of link band- width requirement on average compared to the existing algorithms.
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Networks on chips: a new SoC paradigm
Luca Benini, Giovanni De Micheli · Computer · 2002 · 3.7K citations · Full text
Hardware Security, System On Chip, Design Space Exploration +14
William J. Dally, Brian Towles · 2001 · 3.2K citations
Engineering, Network Routing, On-chip Interconnection Networks +20
A network on chip architecture and design methodology
Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen et al. · 2003 · 1.2K citations