1994 · 72 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMemoryMicroelectronicsDynamic Power ReductionMemory DevicesMemory Hierarchy DesignMemory ManagementMemory Subsystem DesignPower ManagementEnergy-efficient Memory DesignLow-power Memory ArchitectureLow-power Memory CircuitsMemory Circuit DesignMemory CircuitsMemory Power OptimizationOperating ConditionsPower-efficient Memory Design
Memories contain large arrays with high capacitance bitlines and IO lines. To reduce the power of memory accesses we limit the swings on these by controlling the time the lines are driven by using a replica feedback. The swings are set to 10% of the supply over a wide range of process and operating conditions. Introduction Memory power is an important component of the power budget in today's electronic systems. This paper looks at circuit techniques that can be used to reduce the power requirements of a wide access width memory while having minimum effect on its access time. In CMOS memories the access path can be broken into two parts: from address to local wordline select, and from local wordline to sensed data. It is usually the latter half of the access (which involves driving the bitlines and local bus lines and sensing them) that consume the most power. These lines are heavily loaded and thus require a large amount of energy each time they are changed. While various techniques...