Silicon RibbonFET CMOS at 6nm Gate Length

Abstract

Gate-all-around Silicon RibbonFET CMOS transistors at gate length <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{L}_{\mathrm{G}})$</tex> of 6nm are demonstrated and comprehensively characterized. Single Nanoribbon (1NR) vehicle disconnected from subfin is developed to accurately evaluate “true” short channel effect and performance as a function of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{G}}$</tex> and Silicon thickness <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{T}_{\text{si}})$</tex>. NR <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{si}}$</tex> scaling demonstrated to improve short channel effect without penalty to performance down to 3nm, below which, surface roughness scattering degrades transport. Effective workfunction engineering is performed to reduce threshold voltage at highly scaled gate length and compensate for threshold voltage increase due to quantum confinement at scaled <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{si}}$</tex>. Injection velocity <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{v}_{\mathrm{x}0})=1.13\mathrm{x}10^{7}\text{cm}/\mathrm{s}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{G}}=6\text{nm}$</tex> with no degradation down to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{si}}=3$</tex> nm is demonstrated. These key highlights pave the path for continued gate length scaling which is one of the key foundational cornerstones of Moore's law.