Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900μA/μm at Lg<50nm

Abstract

This work builds on the existing research to improve viability of two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a replacement for Si in ultra-scaled nanosheet transistors. We focus on the fabrication of Gate-All-Around (GAA) 2D NMOS and PMOS transistors with scaled gate length (Lg, =S-to-D distance) down to 30nm and specific focus on gate oxide (GOx) module development. Our unique GOx process and refined gate cleans show improved interface quality over both channel and contacts. This results in improved GAA device performance with record SS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 75\text{mV}/\text{dec}$</tex> and Idmax <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt; 900\mu \mathrm{A}/\mu \mathrm{m}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Lg} &lt; 50\text{nm}$</tex> using sub-1-nm-thick monolayer MoS<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> channels. The median DIBL at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Lg}\sim 60\text{nm}$</tex> is as low as 17mV/V but gradually increases to 177mV/V at Lg~30nm attributed to short channel effects. This shows continued advancements on 2D interface quality control and EOT scaling are needed to bridge the gap with Si data and the TCAD computed ideal.