Optimizing the Deployment of Tiny Transformers on Low-Power MCUs

Abstract

Transformer networks are rapidly becoming State of the Art (SotA) in many fields, such as Natural Language Processing (NLP) and Computer Vision (CV). Similarly to Convolutional Neural Networks (CNNs), there is a strong push for deploying Transformer models at the extreme edge, ultimately fitting the tiny power budget and memory footprint of Micro-Controller Units (MCUs). However, the early approaches in this direction are mostly ad-hoc, platform, and model-specific. This work aims to enable and optimize the flexible, multi-platform deployment of encoder Tiny Transformers on commercial MCUs. We propose a complete framework to perform end-to-end deployment of Transformer models onto single and multi-core MCUs. Our framework provides an optimized library of kernels to maximize data reuse and avoid unnecessary data marshaling operations into the crucial attention block. A novel Multi-Head Self-Attention (MHSA) inference schedule, named Fused-Weight Self-Attention (FWSA), is introduced, fusing the linear projection weights offline to further reduce the number of operations and parameters. Furthermore, to mitigate the memory peak reached by the computation of the attention map, we present a Depth-First Tiling (DFT) scheme for MHSA tailored for cache-less MCU devices that allows splitting the computation of the attention map into successive steps, never materializing the whole matrix in memory. We evaluate our framework on three different MCU classes exploiting ARM and RISC-V Instruction Set Architecture (ISA), namely the STM32H7 (ARM Cortex M7), the STM32L4 (ARM Cortex M4), and GAP9 (RV32IMC-XpulpV2). We reach an average of 4.79 <inline-formula><tex-math notation="LaTeX">$\times$</tex-math></inline-formula> and 2.0 <inline-formula><tex-math notation="LaTeX">$\times$</tex-math></inline-formula> lower latency compared to SotA libraries CMSIS-NN (ARM) and PULP-NN (RISC-V), respectively. Moreover, we show that our MHSA depth-first tiling scheme reduces the memory peak by up to 6.19 <inline-formula><tex-math notation="LaTeX">$\times$</tex-math></inline-formula>, while the fused-weight attention can reduce the runtime by 1.53 <inline-formula><tex-math notation="LaTeX">$\times$</tex-math></inline-formula>, and number of parameters by 25%. Leveraging the optimizations proposed in this work, we run end-to-end inference of three SotA Tiny Transformers for three applications characterized by different input dimensions and network hyperparameters. We report significant improvements across the networks: for instance, when executing a transformer block for the task of radar-based hand-gesture recognition on GAP9, we achieve a latency of <inline-formula><tex-math notation="LaTeX">$0.14 \textrm{ms}$</tex-math></inline-formula> and energy consumption of <inline-formula><tex-math notation="LaTeX">$4.92 \boldsymbol{\mu}\textrm{J}$</tex-math></inline-formula>, 2.32 <inline-formula><tex-math notation="LaTeX">$\times$</tex-math></inline-formula> lower than the SotA PULP-NN library on the same platform.