First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel

Abstract

In this letter, we provide the first experimental demonstration of 3D-stacked 2T0C DRAM cells based on indium tin oxide (ITO) FETs. The 3D sequential integration process steps cause negligible performance degradation to the bottom ITO FET including on-current, on/off ratio, subthreshold slope, and mobility, exhibiting excellent stability during the fabrication process of the top FET. Both layers of FETs show very small threshold voltage V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift under positive bias stress measurement for 3,000 s, where the negative shift of V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> is only about 0.045 V and 0.08 V for the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> and 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> layer FETs, respectively. The 3D-stacked 2T0C DRAM cell consisting of two ITO FETs shows excellent data retention time of 1,360 s and endurance over 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup>, rivaling the counterparts based on planar structures. These results indicate the great potential of the 3D-stacked 2T0C DRAM cells for future 3D DRAM applications.