Frontiers in High Performance Computing · 2025 · 11 citations · 25 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designMachine LearningAccelerator ArchitectureData Movement OptimizationDataflow ModelingDeep LearningHardware AccelerationReconfigurable AcceleratorsAcceleratorsConvolutionConvolution Engine DesignDataflow ArchitecturesDeep Learning AcceleratorsEnergy ConsumptionEnergy-efficient Hardware AccelerationThroughput
This paper introduces FlexNPU, a Flex ible N eural P rocessing U nit, which adopts agile design principles to enable versatile dataflows, enhancing energy efficiency. Unlike conventional convolutional neural network accelerator architectures that adhere to fixed dataflows (such as input, weight, output, or row stationary) to transfer activations and weights between storage and compute units, our design revolutionizes by enabling adaptable dataflows of any type through configurable software descriptors. Considering that data movement costs considerably outweigh compute costs from an energy perspective, the flexibility in dataflow allows us to optimize the movement per layer for minimal data transfer and energy consumption, a capability unattainable in fixed dataflow architectures. To further enhance throughput and reduce energy consumption in the FlexNPU architecture, we propose a novel sparsity-based acceleration logic that utilizes fine-grained sparsity in both the activation and weight tensors to bypass redundant computations, thus optimizing the convolution engine within the hardware accelerator. Extensive experimental results underscore a significant improvement in the performance and energy efficiency of FlexNPU compared to existing DNN accelerators.
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