Processing Technologies for GaAs Memory LSIs

Y. Ishii, M. Ino, M. Idda, M. Hirayama, Masamichi Ohmori

1984 · 25 citations · 0 references

Concepts

Abstract

A 16 Kb GaAs static random access memory (SRAM) has been designed adopting direct coupled FET logic (DCFL) circuitry for the main and has been fabricated using self-aligned MESFETs with Self-Aligned Implantation for Ν <sup>+</sup> -layer Technology (SAINT). This SRAM consists of more than 10 <sup>5</sup> FETs, the largest integrated scale m GaAs ICs. A minimum address access time of 4.1 ns has been achieved with a total power dissipation of 2.52 W.