Optimized IGZO FETs for Capacitorless DRAM with Retention of 10 ks at RT and 7 ks at 85 °C at Zero V_hold with Sub-10 ns Speed and 3-bit Operation

Abstract

The emerging capacitorless DRAM based on amorphous oxide semiconductor shows encouraging retention performance, while great challenges still exist in the need of a negative hold voltage and the low on-current with slow write speed. In this work, a BEOL-compatible capacitorless (2T0C) DRAM cell based on optimized amorphous IGZO FETs as write transistors is demonstrated, with a record high retention time and fastest write operation. optimized IGZO transistors at high positive threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> ) over 1.2 V exhibit improved on-current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> ) of 24 $\mu$A/$\mu$m owing to the insertion of a thin In-rich ITO interlayer at source/drain area with greatly reduced contact resistance, enabling sub-ten-nanosecond speed. The high V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> enables remarkable retention time for the 2T0C DRAM cell at zero hold voltage, capable of keeping data over a record-long 10 ks and 7 ks retention time at room temperature and 85°C, respectively. Furthermore, 3-bit memory operations with high linearity are achieved by changing the WBL voltage or WWL voltage at temperatures up to 85°C.