A computing-in-memory macro based on three-dimensional resistive random-access memory

TLDR

Non‑volatile computing‑in‑memory macros based on two‑dimensional memristor arrays are useful for AI edge devices, but scaling to three dimensions offers higher parallelism, capacity, and density while presenting manufacturing and device variability challenges. The authors aim to demonstrate a two‑kilobit non‑volatile computing‑in‑memory macro built on a three‑dimensional vertical resistive random‑access memory. The macro is fabricated using a 55 nm CMOS process and implements 3D vector–matrix multiplication with 8‑, 9‑, and 22‑bit input, weight, and output data. The macro achieves 8.32 tera‑operations per second per watt at 58.2 bit µm⁻² density, and delivers more accurate brain MRI edge detection and higher CIFAR‑10 inference accuracy than conventional methods.

Abstract

Abstract Non-volatile computing-in-memory macros that are based on two-dimensional arrays of memristors are of use in the development of artificial intelligence edge devices. Scaling such systems to three-dimensional arrays could provide higher parallelism, capacity and density for the necessary vector–matrix multiplication operations. However, scaling to three dimensions is challenging due to manufacturing and device variability issues. Here we report a two-kilobit non-volatile computing-in-memory macro that is based on a three-dimensional vertical resistive random-access memory fabricated using a 55 nm complementary metal–oxide–semiconductor process. Our macro can perform 3D vector–matrix multiplication operations with an energy efficiency of 8.32 tera-operations per second per watt when the input, weight and output data are 8, 9 and 22 bits, respectively, and the bit density is 58.2 bit µm –2 . We show that the macro offers more accurate brain MRI edge detection and improved inference accuracy on the CIFAR-10 dataset than conventional methods.