A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

Abstract

This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce channel power consumption. Direct 4-tap decision feedback equalizer (DFE) with timing calibrated reset-less slicer at receiver (RX) and asymmetric bidirectional T-coil are employed to achieve the highest data-rate among the state-of-the-art DRAM I/Os. The prototype chip is fabricated in mimicked 10-nm class DRAM process using 28-nm CMOS. At sub-1V VDDQL, measured TX common eye window is 0.31UI. Measured RX shmoo has total of 162 pass ticks, each tick with the size of 5mV * 1ps and BER under 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> . The total energy efficiency of 2.02pJ/b was achieved.