A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

Abstract

This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.