2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 11 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingMicroelectronicsBuilt-in Self-testDesign For TestabilityError CorrectionError DetectionHardware Fault ToleranceMemory Subsystem DesignAt-speed TestingError ControlHigh Bandwidth MemoryLogic Built-in Self-testMemory Built-in Self-testMemory Fault ToleranceMicroprocessor Built-in Self-testOn-chip Memory Design
This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.
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Ultra-Performance Pascal GPU and NVLink Interconnect
Denis Foley, John M. Danskin · IEEE Micro · 2017 · 213 citations