2003 · 11 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog Integrated CircuitsClock ManagementClock SynchronizationCmos Circuit DesignJitter AnalysisMixed-signal Integrated Circuit DesignClock Data RecoveryClock RecoveryDelay-locked LoopsJitterJitter Tolerance
A 3.125Gb/s clock recovery circuit in 0.18/spl mu/m CMOS comprises a multiplying delay-locked loop (MDLL), an injection-locked slave oscillator and a phase control unit. Injection locking reduces MDLL clock distortion and varies the delay of the recovered clock, while a frequency loop in the phase control unit ameliorates the trade off between phase wander and frequency tolerance. Experimental results show high frequency jitter tolerance is improved by 0.08UI.