IEEE Journal of Solid-State Circuits · 1991 · 18 citations · 5 references
EngineeringVlsi DesignMultimedia ProcessorComputer ArchitectureSystem-level DesignIntegrated CircuitsProcessor ArchitectureHardware SystemsParallel ArchitectureMixed-signal Integrated CircuitTtl-compatible I/o InterfaceParallel ComputingElectrical EngineeringPipelined DateComputer EngineeringPower DissipationComputer ScienceMicroelectronicsCo-processorsVlsi ArchitectureParallel ProgrammingDigital Circuit Design
A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8- mu m BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm*15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A 300-MOPS Video Signal Processor With A Parallel Architecture
Taichi Minami, H. Yamauchi, Y. Tashiro et al. · 1991 · 40 citations
A 50 ns video signal processor
Shinichi Nakagawa, H. Terane, Takeshi Matsumura et al. · 2003 · 19 citations
A BiCMOS channelless masterslice with on-chip voltage converter
Hiroya Fukuda, S. Horiguchi, M. Urano et al. · 2003 · 17 citations
Low-power Electronics, Electrical Engineering, Engineering +15
A single-chip 16-bit 25 ns realtime video/image signal processor
Koichi Kikuchi, Y. Nukada, Yuuichi Aoki et al. · 2003 · 12 citations
Conventional Cmos Logic, System On Chip, Single-chip 16-Bit 25 +14