2004 · 14 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsComputer ArchitectureDigital CommunicationClock ManagementCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDigital Signal ProcessingI/o ArchitectureMixed-signal Integrated Circuit DesignAdaptive EqualizationCmos Analog Integrated CircuitsEqualizationLinear Filter DesignOffset CancellationReceiver ArchitectureReceiver Design
An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13/spl mu/m CMOS. The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.
2