IEEE Solid-State Circuits Magazine · 2019 · 27 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsDelay ModelingTiming AnalysisTiming ModelingAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersAsynchronous Circuit DesignAsynchronous Digital Circuit DesignMetastabilityMetastability AnalysisMetastability Mitigation
This article is the second part of our tutorial on metastability in successive approximation register (SAR) analog-to-digital converters (ADCs). Having covered the synchronous topology in Part I in the Spring 2019 issue of IEEE Solid-State Circuits Magazine, we now investigate its asynchronous (or self-timed) counterpart. Even though the idea of successive approximation is rather old, it was not until 2006 that the benefits of asynchronous timing were unleashed through a seminal contribution by Chen et al. [1]. Since then, the asynchronous variant has emerged as a very popular option to achieve higher speeds and tame metastability issues more gracefully. The latter aspect is the focus of this article.
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Fourteen ways to fool your synchronizer
Ran Ginosar · 2003 · 203 citations
Engineering, Computer Engineering, Electrical Engineering +16
A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS
Ron Kapusta, Junhua Shen, S. Decker et al. · IEEE Journal of Solid-State Circuits · 2013 · 135 citations
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