Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 · 2002 · 46 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsFault-tolerant ComputingBuilt-in Self-testDesign For TestabilityInstruction Set ArchitectureProcessor Core DesignSoftware TestingEmbedded Processor DesignEmbedded TestabilityFault CoverageFault SimulationMicroprocessor Built-in Self-testOutput AnalysisPerformance DegradationTest Generation
A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor self-testing approaches. Test generation and output analysis are performed by utilizing the processor functional modules like accumulators (arithmetic part of ALU) and shifters (if they exist) through processor instructions. No extra hardware is required and there is no performance degradation.
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Accumulator based deterministic BIST
Rainer Dorsch, H.-J. Wunderlich · 2002 · 84 citations
Engineering, Computer Engineering, Electrical Engineering +13
Built-in Self-Test for Digital Integrated Circuits
Vishwani D. Agrawal, Chih‐Jen Lin, Paul W. Rutkowski et al. · AT&T Technical Journal · 1994 · 61 citations
Engineering, Computer Engineering, Electrical Engineering +11
Arithmetic built-in self-test for embedded systems
M. Stojev · Microelectronics Journal · 1998 · 57 citations