2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 12 citations · 4 references
EngineeringElectrical EngineeringAnalog ElectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignMixed-signal IntegrationAdaptive Signal ProcessingAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersBackground CalibrationDynamic Power DissipationGain
Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC. With background calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V. Active area is 12.5mm/sup 2/ in 0.35/spl mu/m CMOS.
4
Time interleaved converter arrays
W.C. Black, D.A. Hodges · 1980 · 75 citations
Engineering, Computer Engineering, Electrical Engineering +16