Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition · 2003 · 34 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsCircuit TheoryMicroelectronicsCmos Circuit DesignIntegrated Circuit DesignRouting ArchitectureVery-large-scale Integration LayoutAnalog Layout DesignAnalog Layout TechniquesCapacitanceCapacitance EstimationCapacitance ModelingCapacitorsCmos Analog Integrated CircuitsLayout Techniques
The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling identical size unit capacitors in a common-centroid geometry. In this paper, a general algorithm for fitting arbitrary capacitor ratios in a common-centroid unit-capacitor array is presented. The algorithm gives special care to both non-integer and identical ratios in order to minimize mismatch. A method for capacitance mismatch estimation based up-on an oxide gradient model is also introduced. It enables the comparison of different unit-capacitor array assignments. Layout issues are discussed with emphasis on a generic routing model. Both the algorithm and the mismatch estimation method are implemented in an automatic capacitor array generation tool.
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