2002 · 15 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemoryMicroelectronicsBuilt-in Self-testMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignUnified Memory SystemsHierarchical Memory ArchitectureHigh Bandwidth MemoryMemory Built-in Self-testMemory CapacityMemory Circuit DesignMemory CircuitsSynchronous MemoryUnified Memory
This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.
3
A 34 ns 256 Mb DRAM with boosted sense-ground scheme
M. Asakura, T. Ohishi, M. Tsukude et al. · 2002 · 23 citations
Engineering, Computer Engineering, Electrical Engineering +14