Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

TLDR

In deep sub‑micron ICs, growing on‑die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems, with soft and hard errors rising and single error events more likely to cause large‑scale multi‑bit errors, yet conventional protection cannot detect or correct such errors without large overhead. The authors propose two‑dimensional (2D) error coding in embedded memories, a scalable multi‑bit error protection technique to improve memory reliability and yield. The scheme uses vertical error coding across words for correction, combined with conventional per‑word horizontal coding. Evaluation on two chip‑multiprocessor cache hierarchies shows 2D coding corrects clustered 32×32‑bit errors while reducing performance, area, and power overheads compared to conventional methods.

Abstract

In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error events are more likely to cause large-scale multi- bit errors. However, conventional memory protection techniques can neither detect nor correct large-scale multi-bit errors without incurring large performance, area, and power overheads. We propose two-dimensional (2D) error coding in embedded memories, a scalable multi-bit error protection technique to improve memory reliability and yield. The key innovation is the use of vertical error coding across words that is used only for error correction in combination with conventional per-word horizontal error coding. We evaluate this scheme in the cache hierarchies of two representative chip multiprocessor designs and show that 2D error coding can correct clustered errors up to 32times32 bits with significantly smaller performance, area, and power overheads than conventional techniques.