2021 IEEE International Electron Devices Meeting (IEDM) · 2021 · 19 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingIntegrated Circuit DesignLeakage Power ReductionPhysical DesignCmos ScalingDevice Width AdaptationEmbedded MemoryGate Oxide InterfacesLeakageMemory Circuit DesignNon-volatile MemoryStatic Random-access Memory Design
For the first time in the industry, 18nm FDSOI technology platform meeting the performance target for next MCU is presented based on triple gate oxide and HKMG process. To meet the performance target of next MCU, continuous-active and device width increase by “contact on gate over active” with wide process margin are utilized. Good yield in 64Mb SRAM array for all SRAM bitcells (bitcell area 0.102um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.124um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for ultra low leakage and high speed, respectively) including ultra low leakage bitcell with retention leakage under 1pA is confirmed. 500hrs HTOL for all SRAM bitcells and WLR for all SG/EG/eZG in TGO are passed. ePCM (embedded Phase Change Memory) is co-integrated in 18nm FDSOI process as non-volatile memory option.
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