Dual gate synthetic MoS₂ MOSFETs with 4.56µF/cm² channel capacitance, 320µS/µm Gm and 420 µA/µm Id at 1V Vd/100nm Lg

Abstract

We have engineered dual gate (DG) MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> transistors with scaled top and back gate stacks based on a surface physisorption ALD approach. A GdAlO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> interfacial layer (IL) between the TMA ‘soak’ seed and the HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> layer has been introduced to improve Vt control, hysteresis, and long channel mobility. Connected dual gate MOSFET with 1-2ML MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> channel reaches <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$420 \mu \mathrm{A}/\text{um}$</tex> drain current and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.56 \mu \mathrm{F}/\text{cm}^{2}$</tex> capacitance at 2.6V gate bias <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\sim 5\times 10^{13}/\text{cm}^{2}$</tex> sheet charge density).