CFET Design Options, Challenges, and Opportunities for 3D Integration

Abstract

Design details of standard cell architectures using complementary field effect transistors (CFET) are explored. The primary structural elements of CFET are reviewed and the layout impact of several 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order technology constructs is analyzed. A manufacturability assessment and cost analysis of the resulting CFET technology-architecture definition is presented. Finally, the extendibility of CFET to 3.5-track cell height as well as higher-order 3D integration is explored.