Novel Analog in-Memory Compute with > 1 nA Current/Cell and 143.9 TOPS/W Enabled by Monolithic Normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS Technology

Abstract

We have developed a method for V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> stabilization in normally-off CAAC-IGZO FETs (OSFETs), and successfully demonstrated analog multiplier circuits and high-efficiency 256-kbit analog in-memory compute (AiMC) chips, which utilize low-leakage OSFETs that retain the gate voltage of Si CMOS devices to drive them in the subthreshold region, for the first time. The novel AiMC chip is monolithically fabricated with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Si\ CMOS+Zn\text{-}rich\ OSFETs$</tex> . This AiMC chip achieves an ultra-low cell current ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;1\ nA/cell)$</tex> , an operation efficiency of 143.9 TOPS/W, and an inference accuracy of over 90% even 30 hours after weight refresh.