Ultra-Deep Annular Cu Through-Silicon-Vias Fabricated Using Single-Sided Process

Abstract

Ultra-deep through-silicon-vias (TSVs) are of great demand for 3D heterogeneous integration. However, most reported deep TSVs adopt double-sided silicon etching and electroplating, which dramatically increases the complexity and cost of the fabrication process. This letter focuses on how to achieve a high-quality Cu seed layer in ultra-deep vias, which is the key technology for the fabrication of single-sided ultra-deep TSVs. By proposing a novel pulsed ultrasound-assisted electroless plating method, continuous and dense Cu seed layers are successfully deposited in silicon vias with a depth as large as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$580 ~\mu \text{m}$ </tex-math></inline-formula> . Combined with a conformal Cu electroplating and a vacuum-assisted Benzocyclobutene (BCB) refilling, BCB-core annular Cu TSVs with depths up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$580 ~\mu \text{m}$ </tex-math></inline-formula> and aspect ratios up to 8 are successfully fabricated. Measured results show that the fabricated TSVs exhibit a depletion capacitance of 1.75 pF, a low leakage current of 0.44 pA at 20 V, indicating good electrical properties.