An Over-Cell Gate Array Channel Router

Abstract

A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. Macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. Each loose horizontal channel segment is assigned to a channel track using a maze router. Vertical channel segments are completed by a modified dogleg channel router.