Impact of Negative Gate Bias and Inductive Load on the Single-Pulse Avalanche Capability of 1200-V SiC Trench MOSFETs

Abstract

In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration.