Digital Gate Driving (DGD) is Double-Edged Sword: How to Avoid Huge Voltage Overshoots Caused by DGD for GaN FETs

Abstract

In this paper, a problem of huge voltage overshoots (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OVERSHOOT</inf> ) of VDS in GaN FETs, which rarely happens during an automatic search of optimum gate driving parameters in a digital gate driving (DGD), is clarified for the first time, and a solution to avoid the problem is proposed. The highest V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OVERSHOOT</inf> in 165k measurements, where parameters of 6-bit DGD IC in 6 time slots in 3.3-ns time intervals are randomly changed in the turn-off of GaN FET at 20 V and 10 A, is 27.6 V, which is 115% larger than the conventional single-step gate driving (CSG) and is almost equal to the maximum rated voltage of the GaNFET. To solve the problem, a safe and fast search method of optimum parameters for DGD is proposed, which achieved 61% reduction of the switching loss and 59% reduction of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OVERSHOOT</inf> compared with CSG.