A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement

Abstract

This article presents a 15-bit quadrature digital power amplifier (DPA) with in-phase and quadrature (IQ)-cell-sharing and transformer-based Doherty operation, which compensates the 3-dB power loss in traditional quadrature architecture and enhances efficiency. Efficiency enhancement at 3-/6-dB power backoffs (PBOs) is obtained on the IQ complex plane to improve average efficiency. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is implemented for compact die size. Fabricated in a 55-nm CMOS technology, the DPA is powered by 1.2-/2.4-V supply voltages and the core circuit only occupies 1.05 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.14-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. It achieves 29.3-dBm peak output power with power added efficiency (PAE) of 43.1%. With 10-MHz 64-quadratic-amplitude modulation (QAM) local thermal equilibrium (LTE) signal, the DPA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {avg}}$ </tex-math></inline-formula> of 23.62 dBm and the average PAE of 24.4% with −25.6-dB error vector magnitude (EVM) at 0.85 GHz without using any digital predistortion (DPD) technique. Moreover, for 20-MHz 64-QAM wireless local area network (WLAN) signal, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {avg}}$ </tex-math></inline-formula> of 21.01 dBm and the average PAE of 20.1% are obtained with −25.1-dB EVM.