UVM Verification IP for AXI

Abstract

Over time, the complexity of ICs design increasing which making these designs more error-prone. Verification of Integrated Circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog UVM methodology gives building blocks and OOP concepts to work with. That allows to create much more flexible test environment with reusable components. This paper presents a verification architecture of configurable Verification IP for AXI interface. This paper presents an architecture of verification environment for AMBA AXI interface and can be used to test any AXI device. A functional coverage model has been developed to determine if the verification process covers all possible scenarios or not. Each testcase reports coverage which is later used to analyze the effectiveness of the testcase. Full coverage has been achieved using both random and directed test cases. The coding is done using System Verilog and the simulation is done using VCS.