An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications

Low-Power CMOS Digital Design

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Low-power CMOS digital design

Anantha P. Chandrakasan, Samuel Sheng, R.W. Brodersen · IEEE Journal of Solid-State Circuits · 1992 · 2.2K citations

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Design and Analysis of Approximate Compressors for Multiplication

Amir Momeni, Jie Han, Paolo Montuschi et al. · IEEE Transactions on Computers · 2014 · 620 citations · Full text

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

Sumeer Goel, Ashok Kumar, Magdy Bayoumi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2006 · 447 citations

Engineering, Computer Engineering, Electrical Engineering +17

CMOS Full-Adders for Energy-Efficient Arithmetic Applications

M. Aguirre-Hernandez, Mónico Linares Aranda · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 348 citations

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