Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

Abstract

Abstract Highly efficient Hamming distance (HD) computations can significantly boost up modern data‐intensive algorithms. However, the traditional complementary metal–oxide–semiconductor devices configured circuits suffer from the huge power consumption with periphery complexity for HD computations. Herein, the implementation of highly reliable and energy efficient in‐memory HD computations in 1 Kb 1‐transistor‐1‐memristor (1T1M) TiN/HfO x /TaO x /TiN array chip is reported. 1T1M devices demonstrate a high on/off ratio of 50, high programming speed of 20 ns, and low energy consumption of 0.224 pJ bit −1 . By modulating the 1T1M cell gate and source signal synergistically, the characteristic XOR operations of the binary information are executed in a reliable manner. Importantly, equipped with a stable low resistance state (LRS) distribution (coefficient of variation <11%), the developed 1T1M arrays can implement accurate HD computations between two 8‐bit strings and simultaneously store computing results in the memristors. The complementary studies demonstrate that the stable LRS is attributed to the TaO x built‐in compliance layer which facilitates the transistor surge current reduction during forming and SET, elaborating the significant potential for achieving reliable in‐memory HD computations. Such architecture manifests a 5‐ and 36.89‐fold enhancement of the processing latency and energy efficiency in comparison with latest reports, promoting the fan out of new in‐memory computing applications.