Wakeup-Free and Endurance-Robust Ferroelectric Field-Effect Transistor Memory Using High Pressure Annealing

Abstract

Wakeup-free and endurance-robust HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric field-effect transistor (FeFET) was fabricated on a silicon-on-insulator substrate. After a high-pressure forming gas annealing as the last alloy step, the performance and endurance of the FeFETs were significantly improved by trap states reduction, polarization enhancement, and wake-up elimination. As the result, the FeFETs show superior endurance exceeding 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cycles and robust retention behavior at program/erase biases of ±3.5V and pulse width of 100 ns. These results indicate that appropriate thermal treatment for the interlayer and ferroelectric material could substantially improve FeFET performance and reliability.