Challenges toward Low-Power SOT-MRAM

Abstract

Spin-orbit-torque magnetic random-access memory (SOT-MRAM) equipped with sub-I-V switching voltage [1, 2] is considered to be one of the promising candidates for next-generation low-power, high speed and non-volatile embedded cache memory applications. To fulfill these performance requirements, however, there are many technical bottlenecks to be conquered, such as SOT efficiency and scalability. This paper presents the recent progress on SOT-MRAM exploration of CMOS compatible high spin-Hall conductivity materials and structures.