Slack redistribution for graceful degradation under voltage overscaling

TLDR

Modern digital IC designs are limited by a critical operating point, or “wall of slack”, that constrains voltage scaling, and overscaling below this point causes timing errors that cannot be adequately detected or corrected, thereby limiting the trade‑off between reliability and power. The authors propose a design‑level approach to trade off reliability and voltage (power) in microprocessor designs. They increase the acceptable voltage range by applying power‑aware slack redistribution that shifts timing slack of frequently exercised, near‑critical paths in a power‑ and area‑efficient manner. The approach heuristically minimizes the voltage at which the maximum allowable error rate occurs, yielding up to 32.8% (average 12.5%) power savings at a 2% error rate with no more than 2.7% area overhead, and enabling more graceful failure.

Abstract

Modern digital IC designs have a critical operating point, or “wall of slack”, that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a design-level approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to fail more gracefully. Compared with baseline designs, we achieve a maximum of 32.8% and an average of 12.5% power reduction at an error rate of 2%. The area overhead of our techniques, as evaluated through physical implementation (synthesis, placement and routing), is no more than 2.7%.