IEEE/ACM International Conference on Computer-Aided Design · 1992 · 65 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware Description LanguagesSystem-on-chip DesignDelay ModelingHigh-level SynthesisLogic SynthesisStandard Cell DesignTiming AnalysisTiming ModelingAsynchronous Circuit DesignCycle TimeFinite-state Machine SynthesisHardware Finite State Machine SynthesisHardware SynthesisLogic MinimizationLogic Minimization Under ConstraintsMinimization
An automatic synthesis tool (3D) for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation, is described. An algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization are presented. The effectiveness of the 3D implementation and the synthesis procedure on numerous designs including a large realistic example (asynchronous data transfer protocol of the SCSI bus controller) is demonstrated. The latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8- mu m CMOS standard cell library are estimated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
Peter Vanbekbergen, Gert Goossens, Francky Catthoor et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992 · 110 citations
Engineering, Computer Engineering, Electrical Engineering +16