IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006 · 94 citations · 30 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign OptimizationInterconnection NetworksGraph AlgorithmsHypergraph TheoryInterconnect DesignMulti-objective Design OptimizationPhysical DesignVery-large-scale Integration LayoutChip PartitioningDomain DecompositionGraph PartitioningGraph-based PartitioningPartitioning AlgorithmsPartitioning In System-on-chip DesignPartitioning StrategiesVery-large-scale Integration
In this paper, we present a family of multiobjective hypergraph-partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both the cut and the maximum subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in very large scale integration (VLSI) computer-aided design (CAD) as they allow to both minimize and evenly distribute the interconnects across the physical devices. Our experimental evaluation on the International Symposium on Physical Design (ISPD98) benchmark show that our algorithms produce solutions, which when compared against those produced by hM/sub E/T/sub I/S have a maximum subdomain degree that is reduced by up to 36% while achieving comparable quality in terms of cut.
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Chameleon: hierarchical clustering using dynamic modeling
George Karypis, Eui-Hong Han, Vipin Kumar · Computer · 1999 · 2.1K citations