2013 · 12 citations · 41 references
ComputingComputer EngineeringComputer ScienceInterconnection NetworksParallel ComputingSystem-on-chip DesignHigh-throughput ComputingInterconnect ArchitectureInterconnect DesignLatency OptimizationNetwork-on-chip DesignSwitching TechniquesBandwidthBroadcastExecution Time AnalysisLow-latency InterconnectsOn-chip InterconnectsParallel Computing InterconnectsSwitch ArchitectureThroughput
Growth in core count creates an increasing demand for interconnect bandwidth, driving a change from shared buses to packet-switched on-chip interconnects. However, this increases the latency between cores separated by many links and switches. In this paper, we show that a low-latency unswitched interconnect built with transmission lines can be synergistically used with a high-throughput switched interconnect. First, we design a broadcast ring as a chain of unidirectional transmission line structures with very low latency but limited throughput. Then, we create a new adaptive packet steering policy that judiciously uses the limited throughput of this ring by balancing expected latency benefit and ring utilization. Although the ring uses 1.3% of the on-chip metal area, our experimental results show that, in combination with our steering, it provides an execution time reduction of 12.4% over a mesh-only baseline.
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