Parallel Computing Interconnects
Parallel Computing Interconnects is a hardware and topology-level architecture that enables high-bandwidth, low-latency communication among processing nodes in parallel computing systems by systematically interconnecting switches and links to support scalable and efficient data exchange.
386
Publications
20.7K
Citations
1.2K
Authors
302
Institutions
Publications per year
2017–2026
23
Parents
386
Sorting networks and their applications
Kenneth E. Batcher · 1968 · 2.4K citations
A Survey of Interconnection Networks
Tse-Yun Feng · Computer · 1981 · 796 citations
Greg Barnes, Rebecca M. Brown, M. Kato et al. · IEEE Transactions on Computers · 1968 · 526 citations
1–5 of 386
1.2K
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University of Illinois Urbana-Champaign, United States
5 publications · 157 citations
5
h-index
1–5 of 1.2K
302
The Ohio State University
Columbus, United States
18 h-index
80 publications
3.9K citations
University of Illinois Urbana-Champaign
Urbana, United States
12 h-index
37 publications
3.8K citations
IBM (United States)
Armonk, United States
11 h-index
55 publications
2.6K citations
Argonne National Laboratory
Lemont, United States
10 h-index
29 publications
887 citations
Los Alamos National Laboratory
Los Alamos, United States
10 h-index
33 publications
1K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
9 h-index
31 publications
2.8K citations
Purdue University West Lafayette
West Lafayette, United States
9 h-index
13 publications
919 citations

Keio University
Tokyo, Japan
7 h-index
17 publications
645 citations
1–8 of 302
16 publications · 2K citations
15
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11 publications · 830 citations
11
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10 publications · 1.6K citations
10
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9 publications · 469 citations
9
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7 publications · 187 citations
7
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