2016 · 19 citations · 9 references
ComputingComputer ScienceHigh-performance ComputingCluster ComputingComputer ArchitectureComputer NetworksCluster ArchitectureCluster InterconnectsCluster NetworkingInterconnect ArchitectureNetwork ArchitectureTorus NetworksGpu InterconnectsHardware Acceleration SupportLow-latency NetworkingParallel Computing InterconnectsScalable Interconnect DesignScalable InterconnectsScalable Network ArchitectureTorus-based Parallel Architectures
We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design allows us to build a low latency, high bandwidth PC cluster, the APEnet+ network, the new generation of our cost-effective, tens-of-thousands-scalable cluster network architecture. Some test results and characterization of data transmission of a complete testbench, based on a commercial development card mounting an AlteraR © FPGA, are provided. 1.
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Fault-tolerant wormhole routing in tori
Suresh Chalasani, Rajendra V. Boppana · 1994 · 52 citations
Pier Stanislao Paolucci, Ahmed Jerraya, Rainer Leupers et al. · 2006 · 51 citations · Full text
Francesco Belletti, Sebastiano Fabio Schifano, R. Tripiccione et al. · Computing in Science & Engineering · 2006 · 38 citations
Computing, Computer Science, Physics +12