A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT

Abstract

It is reported that many cell-internal defects remain undetected when VLSI testing is performed using test sets generated for only traditional fault models like stuck-at faults and transition faults. Therefore, test generation methods for cell-aware, defect-aware, and gate-exhaustive fault models have been proposed to resolve the problem. In all the cases, since the numbers of faults and test patterns can be large, test compaction is very important. In this paper, we propose a multiple target test generation method for gate-exhaustive faults to reduce the number of test patterns using Partial MaxSAT. We aim to generate a test pattern which can detect as many target faults as possible simultaneously by Partial MaxSAT. We also propose a multiple target fault selection method for the test generation using independent fault sets and justification technique. Experimental results on ISCAS'89 benchmark circuits show that the number of test patterns was reduced by 35.39% compared with a conventional method on average.